1. Field of the Invention
The present invention relates to the simulation of integrated circuits (ICs) and in particular to providing a fast simulation method for ICs with power management circuitry.
2. Related Art
As IC technology has shrunk to 90 nm and below, total power consumption has become one of the most important concerns in system-on-chip chip designs. Known techniques such as power gating, voltage scaling, and variable threshold CMOS have been adopted to reduce standby leakage current and dynamic power dissipation. However, as explained below, such techniques pose a significant challenge to both pre-layout and post-layout full chip verification due to the extremely large size of the matrices of the nodal analysis equation sets required for simulation.
A system-on-chip (SoC) design typically includes at least one power supplying module, which has at least one output node that serves as the voltage supplying node of other modules. An exemplary power supplying module may include a charge pump, a regulator, a power switch, and/or a transistor to provide one or more power supplies for the design.
SPICE is a well-known general-purpose circuit simulation program developed by the University of California at Berkeley. SPICE can simulate circuits including, for example, resistors, capacitors, inductors, voltage sources, current sources, transmission lines, and common semiconductor devices. Fast-SPICE simulators use various algorithms to improve performance over traditional SPICE simulators.
One exemplary algorithm to improve performance includes partitioning in which a circuit is broken up into smaller blocks at the boundary of ideal voltage source nodes and weak coupling nodes (e.g. at the gates of MOSFET devices). For example, as shown in FIG. 1A, a conventional fast-SPICE simulator partitions a circuit 100 into two blocks 110 and 111 because both blocks are directly connected to the ideal voltage source. Note that only a limited number of exemplary circuit elements (e.g. transistors and a resistor) are shown in FIG. 1A, whereas an actual circuit would typically include many other circuit elements.
Notably, when using a fast-SPICE simulator blocks 110 and 111 can be simulated at different rates according to their latency during simulation. As a result, a fast-SPICE simulator may provide speed increases of 10×-1000× with acceptable lose of accuracy. However, a fast-SPICE simulator is typically inefficient for SoC circuits because the output node(s) of the power supply module (in FIG. 1A, a power node 102 of a power supply module 101) are non-ideal and therefore the simulator must operate on a large, flattened partition. Specifically, the fast-SPICE simulator must synchronously simulate the circuits within block 111.
Some advanced simulators, such as HSIM, can further partition the large blocks into second-level blocks and then take advantage of the isomorphic matching. For example, as shown in FIG. 1B (which ignores small block 110 (FIG. 1A) for simplicity), an HSIM simulator cuts the circuit 100 at power node 102 and partitions to generate a plurality of channel-connected blocks (CCBs) 101, 103, 104, and 105. Note that simulation tools generally define CCBs at the transistor level. These CCBs are relatively simple circuits (wherein the invertors shown are illustrative, and not limiting).
Because the output node of power supply module 101, i.e. power node 102, is a non-ideal voltage supply source, CCBs 101, 103, 104, and 105 must be evaluated simultaneously (i.e. synchronously) to provide an accurate simulation of power node 102. Because of its size, CCB 105 can be further partitioned by an HSIM simulator. In this example, CCB 105 can be further partitioned into CCBs 106, 107, and 108. Note various simulation tools determine the membership of cut groups (i.e. blocks formed by partitioning) in different ways. For example, in one embodiment, a simulation tool may determine a cut group based on the number of CCBs connected to the cut.
Notably, once again CCBs 106, 107, and 108 must be evaluated synchronously, i.e. these CCBs also form flattened partitions. Thus, CCBs 101, 103, 104, and 105 can be characterized as a first-level cut group, whereas CCBs 106, 107, and 108 can be characterized as a second-level cut group. Note that the evaluation results from CCB 105 can be used in the synchronous evaluation of CCBs 103, 104, and 105. Therefore, despite this hierarchical partitioning, an HSIM simulator typically has sub-optimal, i.e. relatively slow, results when simulating large (e.g. SoC) circuits having non-ideal power supplying modules.
Therefore, a need arises for a fast simulation method for circuits with power management circuitry.